Profile banner
Solanki Parjanya

Solanki Parjanya

ASIC Physical Design intern focused on VLSI backend

Ahmedabad, India
theorg
Joined March 2026
Favicon imagein.linkedin.com
Favicon imageyoutube.com
Favicon imageinstagram.com

Network

935 connections
💡
ASIC Physical Design
👨‍🎓
Maven Silicon Trainees
🎓
LDCE Alumni
✅
VLSI Design Verification
🏗️
eInfochips Physical Design
⚙️
...
👑
Maven Silicon Leadership

Summary

Early-career specialist in VLSI physical design: currently working as an ASIC Physical Design intern and explicitly focused on backend physical design techniques within the VLSI domain. theorg
Completed targeted training in advanced physical design and verification through a Maven Silicon course (2024–2025), indicating formal upskilling in backend/verification methodologies.
Hands-on avionics internship experience: served as an avionics engineer intern at Omspace Rocket & Exploration Pvt. Ltd., with the company publicly acknowledging successful completion of the internship. linkedin
Academic foundation in electronics and communications: holds a B.E. in Electronics and Communications Engineering (L.D. College of Engineering, 2021–2024) with a reported 7.77 CGPA and appears on a provisional PG merit list for VLSI-related postgraduate admission. ac

Work

Education