Dutt Panchal

Final-year Electronics and Communication Engineering student at Dharmsinh Desai University specializing in the end-to-end VLSI design and verification lifecycle. Possesses deep understanding of digital design principles, hardware-software integration, and advanced proficiency in hardware description languages including Verilog, SystemVerilog, and UVM. github+2

Focuses on transforming architectural requirements into efficient RTL code while ensuring design integrity through rigorous simulation and functional verification flows. Proficient in modern verification methodologies including Universal Verification Methodology (UVM) to build scalable, constrained-random testbenches and drive verification closure for complex digital systems. github+2

Professional experience includes a specialized internship in VLSI Design and Verification at Scaledge Technology working on ASIC flows and hardware implementation. Also completed tenure as Verification Trainee at SuchiLogic, deepening expertise in modern verification methodologies. github+2

Seeks opportunities to contribute to cutting-edge chip design teams and collaborate on next-generation semiconductor technology. Committed to staying at the forefront of industry trends in RTL design, functional verification, and EDA automation. canva+1