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Ulhas Kotha

Ulhas Kotha

Director, Timing Signoff Methodologies at NVIDIA

ulhas-kotha
Bengaluru, Karnataka, India
Joined February 2026
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Summary

Experienced timing signoff and static timing analysis leader: Ulhas has a long track record at NVIDIA focused on timing signoff methodologies and STA-related problems, including work named explicitly on Timing Signoff Methodologies and Tempus-IPD signoff. theorg+1
Technical contributor to academic and industry forums: Ulhas has co-authored and presented technical work at venues such as TAU 2019 (on MIS and computation reduction) and appears in conference/poster listings, indicating active participation in the timing/EDA research community. tauworkshop+2
Long engineering career with embedded systems and verification experience: Verified earlier roles include verification and hardware engineering positions at Sun Microsystems and Open-Silicon, plus an early internship at Real Chip, showing foundational experience in hardware verification and design. theorg
Formal engineering education in electrical and telecommunications fields: Holds an M.S. in Electrical Engineering from San José State University and a B.E. in Telecommunication from Dayanand Sagar College of Engineering, forming the academic foundation for his timing and hardware expertise. theorg+1

Work

Education

Projects

Writing

A Graph Based Approach For Computation Reduction For Multi Input Switching

January 1, 2019

Slides/paper presenting a graph-based approach to reduce computation for multiple input switching (MIS) effects in static timing analysis; co-authored by Amartya Mazumdar, Anshuman Seth, and Ulhas Kotha.

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Selected Poster (conference listing including Nvidia authors)

Conference poster listing Ulhas Kotha among Nvidia co-authors on selected poster entries.

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Hobbies

Maintains a personal YouTube channel with playlists for cooking and guitar. youtube

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