Mohan Sardar
Next-Gen Verification Engineer with expertise in VLSI Design
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Work
Education
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Writing
SRAM Memory Design and Verification with SystemVerilog Testbench
October 1, 2023A detailed article describing the process of verifying an SRAM module using a SystemVerilog testbench, including the Verilog code for the SRAM DUT and the SystemVerilog testbench components.
Design of 10110 Digital Sequence Detector in Real-Time using Verilog HDL
October 1, 2023An article explaining the design of a 10110 digital sequence detector implemented using Verilog HDL, including the code and state diagram.
The Crucial Role of Design Verification in Today’s Semiconductor Chips
September 1, 2023An article outlining the importance of design verification in semiconductor chip development, comparing it to quality control, detailing the evolution of chip design, the verification process, and future trends, from an engineer's perspective.
Functional Coverage Notes
A piece discussing the role of functional coverage in the verification of a Device Under Test (DUT), likely related to VLSI verification.
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