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Dr. Ashish Sachdeva

Dr. Ashish Sachdeva

Professor and VLSI researcher focused on low-power SRAM design

rishabchhetri
Mullana, Ambala, Haryana, India
Joined February 2026
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Summary

Established VLSI and low-power memory researcher with a sustained publication record in SRAM, CNTFET and FinFET circuit design. google+1
Active academic with multiple teaching and faculty appointments across Indian universities, holding positions from Assistant Professor to Professor and short-term administrative leadership roles. orcid+2
Engaged in editorial work for scientific publishers, serving on editorial teams and handling manuscripts for journals and publishers. nature+2
Involved in applied research and technology translation activities including patenting and industry-institute liaison work. edu+1

Work

Education

Projects

Writing

A linear cross-coupled gate-driven quasi-floating bulk low-power wide input range transconductor

March 1, 2024

Paper proposing an OTA using a cross-coupled gate-driven quasi-floating bulk MOSFET and source-degenerated linearization for low-power, wide input range bio-signal conditioning; post-layout simulations in 180 nm CMOS and performance/variability analysis.

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Hyperspectral imaging and its applications: A review

January 1, 2024

A 2024 review on hyperspectral imaging and its applications across military, environmental and civil domains (listed among authored/co-authored works).

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Selected World Scientific / journal publications (examples)

Includes multiple journal publications on low-power SRAM cell designs and related VLSI circuit topics (DOI-listed articles on World Scientific pages).

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Conference and journal contributions on CNTFET/FinFET SRAM designs and low-power VLSI

Multiple peer-reviewed articles and conference papers on CNTFET-based SRAM, FinFET SRAM, multi-cell upset immune designs, and low-power memory/analog circuit designs.

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