Jithin Kalangi

Jithin is an aspiring Silicon Design Engineer with a strong academic background in Electronics and Communication Engineering. He is currently a DV Engineer at AMD, with prior experience as a Sr ASIC Digital Design Engineer and ASIC Digital Design Engineer at Synopsys Inc. His career path demonstrates a clear focus on semiconductor technology and digital design verification.

During his university years at Lovely Professional University, Jithin was actively involved in robotics and intelligent systems through the Robotics and Intelligent Systems Community (RISC-LPU). He contributed to innovative projects, participated in hackathons like the Smart India Hackathon where his team 'Electronica' achieved significant success, and presented technical models at events such as the Punjab Innovation and Technology Summit. great-site+1

Jithin has experience in academic research, co-authoring a paper titled 'FIELD FOR SENSING AND GEO- MAPPING OF SOIL PROPERTIES' which was published as part of Anveshan 2020. This highlights his engagement in scientific inquiry and contribution to his field. scribd