
Tannu Sharma
Principal Design Engineer focused on ASIC timing and relative timing
Summary
Work
Education
Projects
Writing
Learning Based Timing Closure on Relative Timed Design
January 1, 2021Exploration of machine-learning based methods to improve timing closure for relative timed circuits, aiming to improve power and performance and reduce overall runtime with commercial EDA tools.
Automatic Timing Closure for Relative Timed Designs
January 1, 2020Algorithm and methodology for automatic convergence of relative timing constraints through synthesis, place-and-route and timing verification flows to create timing-closed designs.
Physical Design Variation in Relative Timed Asynchronous Circuits
January 1, 2017Study of physical design variation impacts on relative timed asynchronous circuits.
Path Based Timing Validation for Timed Asynchronous Design
January 1, 2016Methodology enabling commercial EDA tools to support cyclic path timing validation for timed asynchronous designs, addressing combinational cycles and controller-local timing path identification.
Relative Placement in Timed Asynchronous Design
January 1, 2016Work addressing placement considerations in timed asynchronous design and their effect on timing.