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Tannu Sharma

Tannu Sharma

Principal Design Engineer focused on ASIC timing and relative timing

tannu-shree
Fremont, California, USA
Joined May 2026

Summary

Specialist in timing and relative-timing methodologies for asynchronous and bundled-data circuit designs, with multiple peer-reviewed publications focused on timing validation, timing-closure algorithms, and placement/timing-driven approaches. google+2
Academic researcher who produced PhD-level work at the University of Utah (2014–2019) and contributed several conference and workshop papers on relative timing and asynchronous circuit techniques. utah+1
Transitioned into industry R&D and solutions roles after doctoral studies, holding positions at Synopsys and Cadence and later serving as a Principal Design Engineer at a multigig startup. google+1
Active in student and professional service during graduate studies (listed as IEEE Student Branch vice chair at University of Utah), indicating engagement in student leadership activities while completing graduate research. utah

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