Nayina Ramapur
Application Engineer skilled in VLSI, FPGA, and embedded systems
Summary
Work
Education
Writing
Fusion Based Face Recognition System using 1D Transform Domains
December 1, 2017This paper proposes a fusion-based face recognition system utilizing 1D Discrete Wavelet Transform (DWT) and Fast Fourier Transform (FFT) features. It converts 2D face images to 1D vectors and compares features using Euclidean Distance, then fuses performance parameters at the matching level for improved results.
Reversible Logic-MUX-Multiplier based Face Recognition using Hybrid Features
November 1, 2016This research introduces a novel Reversible Logic MUX-Multiplier (RLMM) for face recognition. It focuses on designing multipliers for edge detection of face images using reversible logic gates, combining steganography, Canny Edge Detection, DWT, and Local Binary Pattern (LBP) with Self Organizing Map (SOM) for feature extraction.
Design of High Speed All Digital Phase Lock Loop for FM Application
June 1, 2015This paper proposes a high-speed All Digital Phase Lock Loop (ADPLL) for FM applications, designed using a phase detector, digital loop filter, and a novel multiplexer-based increment-decrement counter to achieve reduced delay compared to existing ADPLL designs.
SOM based Face Recognition using Steganography and DWT Compression Techniques
This work proposes an SOM-based face recognition system that utilizes steganography for image compression and DWT for initial feature extraction, combined with Local Binary Pattern (LBP). It applies preprocessing techniques like resizing and Gaussian filtering for uniform image quality.