Ishant Bhardwaj
ASIC digital design / design-verification engineer — SerDes & PCIe
New Delhi, Delhi, India
Joined June 2026
Summary
Progressive ASIC digital-design career with increasing seniority at Synopsys. rocketreach
Technical focus spans high-speed SerDes and PCIe-related design and verification topics (mentions include SerDes PHY, PCIe Gen4/5/7, NRZ, PAM4, UVM, GLS). linkedin
Graduate-level specialization in microelectronics at IIT Madras with an M.Tech project listed under identifier EE22M532 and an associated project proposal slide deck. slideshare+1
Foundational VLSI and engineering experience from undergraduate studies and early roles at Whizchip and INVECAS before joining Synopsys. scribd+1