Deepak Kumar

I verify silicon before it costs millions: I design RTL and build rigorous UVM verification environments that stress designs early — for example, in my AXI DMA Controller I implemented independent read/write master channels and verified async clock-domain crossings and 256-beat burst behavior. github+1

My technical toolkit includes SystemVerilog (UVM, SVA), Verilog, Python, and C++; I’m experienced with protocols like AXI, AHB, APB, UART, I2C, and SPI, and tools such as Cadence Xcelium, Xilinx Vivado, and GTKWave.

Selected projects I’ve built and verified: AXI DMA Controller; RISC‑V 5‑Stage Pipeline with a full hazard unit and data forwarding; Synchronous FIFO with a UVM environment reaching 93.75% functional coverage; and a UVM ALU testbench that used AI‑assisted failure triage to cut debug time by ~40%. github+3

I’m a 3rd‑year ECE student at NIT Jalandhar (Class of 2027); having been selected twice for SSB interviews (AFSB Mysore & SSB Allahabad) I bring discipline under pressure, and I’m actively seeking internships in VLSI design or silicon verification for Summer 2026 — let’s connect if you’re building silicon and need someone who cares about verification as much as design.