Profile banner
George Sidiropoulos

George Sidiropoulos

Co-founder and technology executive focused on ultra-low-power GPUs

Patras, Greece

Summary

Technical GPU and SoC architect with deep IP and patent experience justia+2
Founder‑CEO who built an ultra‑low‑power GPU IP company from Patras and led its commercialization metavallon+2
Led Think Silicon through funding, product expansion and acquisition, then continued leadership inside Applied Materials metavallon+2
Focused on embedded and wearable markets—bringing graphics and ML together for ultra-low-power edge devices jonpeddie+1

Work

Education

Projects

Writing

Asymmetric multi-core heterogeneous parallel processing system with content aware and display aware rendering logic

August 1, 2021

Patent covering an asymmetric multi-core heterogeneous parallel processing GPU architecture that partitions workloads among groups of GPU cores with different capabilities to optimize rendering and power.

Favicon imagepatents.justia.com

Framebuffer compression with controllable error rate

August 1, 2020

Patent describing adaptive lossy delta-based compression techniques for framebuffer color data with controllable error rates to reduce memory bandwidth in tile-based rendering systems.

Favicon imagepatents.justia.com

System and method for adaptive z-buffer compression in low power GPUs and improved memory operations with performance tracking

February 1, 2020

Patent for z-buffer compression techniques and related performance-tracking methods to reduce memory usage/bandwidth in low-power GPUs.

Favicon imagepatents.justia.com

Asymmetric multi-core heterogeneous parallel processing system

December 1, 2019

Patent on multi-core asymmetric GPU designs that use core groups with different microarchitectures and power profiles to execute subsets or the full instruction set for power/performance trade-offs.

Favicon imagepatents.justia.com

Adaptive lossy framebuffer compression with controllable error rate

February 1, 2018

Earlier patent variant describing adaptive lossy compression for framebuffer color data driven by a dedicated unit enabling controllable error rates.

Favicon imagepatents.justia.com

Methods for fixed rate block based compression of image data

May 1, 2017

Patent covering methods and hardware for fixed-rate block-based image compression to reduce memory bandwidth and storage for graphics processing systems.

Favicon imagepatents.justia.com