Profile banner
Naveen Pathak

Naveen Pathak

VLSI and FPGA researcher; Junior Research Fellow

New Delhi, DL, India
rocketreach
Joined March 2026

Network

2.8K connections
💻
AMD Silicon Design
✅
VLSI Verification Engineers
🛠️
EDA Application Engineers
🚀
Vicharak Startup Team
🔬
IIT Delhi
⚙️
Intel
📱
Qualcomm Silicon Engineers

Summary

VLSI and FPGA-focused researcher with academic contributions: Naveen completed an M.Tech in VLSI and has authored/co-authored FPGA-focused research and conference papers on FPGA implementations and classifiers. ac+2
Bridges academia and industry: his background includes academic roles (Teaching Assistant, JRF positions) and industry experience (Co-Op at AMD, FPGA R&D at Vicharak, engineering/trainee roles at Punj Lloyd and Jaypee). google+1
Fellowship-supported research and biomedical project involvement: while at IIT Jammu he is listed among staff working on fellowship-funded projects and specifically the Implantable Pacemaker Chip (iPACE-Chip). ic-resq
Early-career researcher with progressive roles: Naveen's recorded history shows successive research and engineering roles from trainee and industry engineer positions through teaching assistantships to multiple junior research fellow appointments. rocketreach+1

Work

Education

Projects

Writing

Study and implementation of mux based FPGA in QCA technology

January 1, 2026

Research on constructing and designing FPGA architectures using MUX-based approaches in Quantum-dot Cellular Automata (QCA) technology.

Favicon imageresearchgate.net

Performance Comparison of FPGA Based Linear SVMS Classifier (and related FPGA works)

January 1, 2023

Contributions to conference proceedings including FPGA-based classifier performance comparisons and online log analysis (co-authored papers listed in proceedings).

Favicon imageproceedings.com